The Challenge of Scaling and the Rise of Tellurium
The relentless pursuit of Moore’s Law—the observation that the number of transistors on a microchip doubles approximately every two years—has forced the semiconductor industry to explore materials beyond traditional bulk silicon. As transistors shrink toward the sub-5-nanometer (nm) regime, silicon faces severe "short-channel effects," where leakage current and power consumption become unmanageable. This has led to the rise of "Post-Silicon" materials, including transition metal dichalcogenides (TMDs) like molybdenum disulfide (MoS2) and elemental 2D materials like tellurium.
Tellurium is particularly prized for its high hole mobility, which is essential for p-type transistors. In modern Complementary Metal-Oxide-Semiconductor (CMOS) logic, both n-type (electron-carrying) and p-type (hole-carrying) transistors are required. While many 2D materials excel as n-type semiconductors, finding a stable, high-performance p-type counterpart has been a historical challenge. Tellurium offers a narrow bandgap, exceptional air stability, and compatibility with Back-End-of-Line (BEOL) integration—a process where transistors are fabricated on top of existing interconnect layers to enable 3D integrated circuits.
However, as tellurium layers are thinned to the ultrathin regime (below 10 nm) to improve gate control, a new problem arises: low-frequency (1/f) noise. This noise acts as a fundamental limit to the sensitivity of sensors and the reliability of logic circuits. Until the publication of the POSTECH research, the exact origin of this noise in ultrathin Te FETs—whether it stemmed from the channel itself or the contact points—remained a subject of intense debate.
Technical Analysis of Contact-Origin Noise
The research team, led by Hae-Won Lee and Byoung Hun Lee, focused their investigation on the 1/f noise characteristics of Te FETs at varying thicknesses. 1/f noise, also known as flicker noise, is a type of electronic noise where the power spectral density is inversely proportional to the frequency. In semiconductors, this noise is typically explained by two primary theories: the Carrier-Number-Fluctuation (CNF) model and the Hooge’s Mobility Fluctuation (HMF) model.
The CNF model suggests that noise is caused by the random capture and emission of charge carriers by traps located near the interface of the semiconductor and the dielectric layer. The HMF model, conversely, attributes noise to fluctuations in the mobility of the carriers themselves due to lattice vibrations or impurities.
In their experiments, the POSTECH researchers compared devices with a 5 nm Te channel to those with a 13 nm channel. They discovered that while the 13 nm devices adhered strictly to the CNF model across various temperatures, the 5 nm devices exhibited significant deviations at room temperature (300 K). Specifically, in the low-current regime, the 5 nm devices showed a surge in noise that could not be explained by simple channel-interface traps.
Through bias-dependent and temperature-dependent analysis, the team identified the culprit: "contact-origin trap-assisted tunneling." When the tellurium layer becomes thinner than the depletion width of the material, the traps at the metal-semiconductor contact interface begin to dominate the electronic behavior. These traps facilitate the tunneling of carriers in a way that introduces excess noise, effectively "polluting" the signal before it even travels through the channel.
Experimental Chronology and Methodology
The development of this research followed a rigorous chronological path of material synthesis, device fabrication, and cryogenic testing:
- Material Synthesis (Late 2024 – Early 2025): The team utilized high-quality tellurium synthesized through physical vapor deposition and solution-based methods to ensure high crystallinity. Tellurium’s chiral chain structure requires precise control during growth to maintain its p-type characteristics.
- Device Fabrication: FETs were constructed using a standard lithography process. The researchers fabricated two sets of control devices—one with a uniform 5 nm thickness and another with a uniform 13 nm thickness—to establish a baseline for noise performance.
- Noise Characterization: Between mid-2025 and late 2025, the team conducted extensive noise measurements. Using a low-noise amplifier and a spectrum analyzer, they measured the drain current fluctuations across a wide range of gate voltages.
- Temperature Dependency Tests: To isolate the noise mechanism, the researchers cooled the devices to 100 K. They observed that at 100 K, the trap activation in the 5 nm devices was suppressed, and the noise behavior returned to the standard CNF model. This confirmed that the "excess" noise at room temperature was thermally activated and localized at the contacts.
- Engineering the Solution: Based on these findings, the team designed a "locally thickened" architecture. They engineered a device where the active channel remained at 5 nm for optimal gate control, but the areas directly beneath the source and drain metal contacts were thickened to 13 nm.
Supporting Data and Performance Metrics
The results of the contact-centric engineering approach were stark and quantifiable. By inserting the locally thickened 13 nm Te layer, the researchers achieved the following:
- Noise Reduction: In the nanoampere (nA) current regime, the noise level was reduced by a factor of ten (one order of magnitude) compared to the standard 5 nm device.
- Model Restoration: The engineered devices restored the CNF behavior at room temperature, indicating that the contact-origin traps were successfully screened from the carrier injection process.
- Bias Independence: The dependence of noise on the drain bias was decreased by approximately twofold. In standard ultrathin FETs, increasing the drain voltage often exacerbates noise; the new design demonstrated much higher stability.
- Threshold Voltage Stability: The thickening of the contact regions did not negatively impact the threshold voltage or the subthreshold swing of the 5 nm channel, preserving the transistor’s efficiency.
The study provides a clear data set showing that the 13 nm "buffer" beneath the contacts acts as a shield. It prevents the depletion region from fully penetrating the ultrathin channel at the contact interface, thereby minimizing the influence of interface traps on the injection of holes.
Industry Implications and Official Context
While the researchers at POSTECH have not issued a joint statement with commercial foundries, the implications of their work are being closely monitored by industry leaders like Samsung Electronics and TSMC. Both companies are currently exploring BEOL-compatible transistors to enable "3D Logic-on-Memory" and other advanced architectures.
Industry analysts suggest that the ability to decouple device scaling from noise is a "holy grail" for 2D semiconductor commercialization. "The transition from 3 nm to 2 nm and eventually 1 nm nodes requires more than just smaller features; it requires quieter features," noted a technical analysis of the POSTECH paper. "By identifying that the contact interface—rather than the material itself—is the primary noise generator in tellurium, this research provides a manufacturable blueprint for high-performance p-type FETs."
The research also aligns with the broader goals of the International Roadmap for Devices and Systems (IRDS), which emphasizes the need for new materials that can operate at low power with high reliability. Tellurium’s compatibility with low-temperature processing makes it an ideal candidate for BEOL, where high temperatures (above 400°C) can damage the underlying copper interconnects and transistors.
Broader Impact on Future Electronics
The successful engineering of low-noise tellurium transistors has ramifications beyond just microprocessors. The findings are expected to influence several key areas of technology:
1. High-Sensitivity Sensing
Low-frequency noise is the primary limiting factor in the "Limit of Detection" for chemical and biological sensors. By utilizing the locally thickened Te architecture, engineers can create ultrathin, flexible sensors capable of detecting trace amounts of molecules with significantly higher signal-to-noise ratios.
2. Quantum Computing Interfaces
As quantum computers require precise control electronics that operate at cryogenic temperatures, the POSTECH team’s findings on temperature-dependent noise suppression provide valuable data for designing interfaces that can bridge the gap between quantum bits (qubits) and classical logic.
3. Energy-Efficient CMOS Logic
The realization of high-performance p-type Te transistors allows for the development of full 2D CMOS circuits. Currently, many experimental 2D circuits are "n-type only," which is significantly less energy-efficient than complementary logic. Integrating the POSTECH noise-reduction strategy could lead to the first commercially viable 2D CMOS chips.
4. Wearable and Flexible Electronics
Because tellurium is air-stable and can be processed at relatively low temperatures, it is a prime candidate for flexible displays and wearable health monitors. The reduction in noise ensures that these devices can maintain accurate readings even as the material undergoes mechanical stress.
Conclusion
The paper "Revealing and Engineering Contact-Origin Noise in Ultrathin Tellurium Transistors" serves as a pivotal correction to previous assumptions regarding noise in 2D materials. By shifting the focus from the channel to the contact interface, the POSTECH researchers have provided a sophisticated yet practical solution to a fundamental scaling problem. As the semiconductor industry moves toward the 2030s, the "contact-centric" engineering approach demonstrated in this study will likely become a standard methodology for integrating a variety of ultrathin semiconductors into the global supply chain, ensuring that the devices of the future are not only smaller but also more reliable and precise.