The pursuit of continued semiconductor scaling has led researchers to explore materials beyond the traditional boundaries of silicon, with Molybdenum Disulfide (MoS2) emerging as a primary candidate for the next generation of sub-2nm transistor channels. A joint research effort between imec, the world-renowned nanoelectronics research hub, and ETH Zurich has resulted in a comprehensive technical study titled "Oxide induced degradation in MoS2 field-effect transistors," published in March 2026 in the journal npj 2D Materials and Applications. The paper, authored by F. Ducry, B. Van Troeye, M. Dossena, and colleagues, provides a critical analysis of the interface between two-dimensional (2D) semiconductor channels and the amorphous gate oxides required for device operation. This research addresses one of the most significant bottlenecks in the commercialization of Transition Metal Dichalcogenides (TMDCs): the performance loss that occurs when these atomically thin materials are integrated with standard dielectric materials like Alumina (Al2O3) and Hafnium Oxide (HfO2).
The Transition to Two-Dimensional Semiconductors
For over five decades, the semiconductor industry has relied on the bulk properties of silicon to drive the exponential growth of computing power, a phenomenon known as Moore’s Law. However, as transistor gate lengths shrink toward the atomic scale, silicon faces insurmountable physical limitations, most notably the loss of electrostatic control and the rise of "short-channel effects." To counteract these issues, the industry has transitioned from planar transistors to FinFETs and, more recently, to Gate-All-Around (GAA) nanosheets. Despite these architectural innovations, the thickness of the channel material remains a limiting factor.
Transition Metal Dichalcogenides, specifically MoS2, offer a solution by providing a naturally thin channel—often just a single molecule thick (approximately 0.65 nm). MoS2 possesses a wide bandgap, making it ideal for low-power logic applications, and its 2D nature allows for superior electrostatic control compared to ultra-thin body silicon or III-V semiconductors. However, the theoretical performance of MoS2 is rarely achieved in practical devices. The primary culprit is the interface between the 2D lattice and the surrounding environment, particularly the gate dielectric.
The Challenge of Oxide-Induced Degradation
The imec and ETH Zurich study focuses on the degradation mechanisms that arise when MoS2 is paired with amorphous gate oxides. In traditional silicon-based transistors, the interface between silicon and silicon dioxide (SiO2) is relatively well-behaved due to the formation of a stable native oxide. In contrast, MoS2 is a van der Waals material; it lacks "dangling bonds" on its surface, which makes it chemically inert but also difficult to coat with other materials.
When high-k dielectrics like Al2O3 or HfO2 are deposited onto MoS2, the resulting interface is often disordered. The researchers utilized first-principles simulations—specifically Density Functional Theory (DFT)—to model how the amorphous structure of these oxides disrupts the electronic properties of the MoS2 channel. The study reveals that the presence of the oxide induces scattering and energy-level fluctuations that significantly lower carrier mobility. This "oxide-induced degradation" is a fundamental hurdle because high-k dielectrics are essential for maintaining gate capacitance without allowing excessive tunneling leakage.
Methodology and Simulation Framework
The researchers employed a rigorous simulation framework to understand the interactions at the atomic level. By comparing monolayer, bilayer, and trilayer MoS2 configurations, the team was able to quantify how the thickness of the semiconductor influences its resilience to oxide-induced interference.
The simulation process involved several key steps:
- Atomic Modeling: Constructing realistic models of amorphous Al2O3 and HfO2 interfaces using "melt-and-quench" molecular dynamics.
- Electronic Structure Analysis: Calculating the band structures and density of states for the MoS2-oxide systems.
- Transport Calculations: Determining how the disorder at the interface impacts the flow of electrons through the channel.
A critical finding of the study was that the amorphous nature of the oxide introduces localized states within the bandgap of the MoS2. These states act as traps for electrons, leading to a reduction in the "on-current" of the transistor and a degradation of the subthreshold swing—a measure of how efficiently a transistor can switch from an "off" to an "on" state.
Comparative Performance: Al2O3 vs. HfO2
The study provides a detailed comparison between two of the most common gate dielectrics used in the semiconductor industry. Alumina (Al2O3) is often used as a seed layer or a primary dielectric in experimental 2D devices due to its relatively large bandgap and stability. Hafnium Oxide (HfO2) is the industry standard for high-performance logic due to its higher dielectric constant (k-value), which allows for thinner equivalent oxide thicknesses (EOT).
The data suggests that HfO2, while offering better electrostatic scaling, tends to induce more significant degradation in the MoS2 channel compared to Al2O3. This is attributed to the higher density of low-energy vibrational modes (phonons) in HfO2 and a more complex interface chemistry that facilitates the formation of "remote phonon scattering" sites. For monolayer MoS2, the impact is most severe, as every atom in the channel is directly exposed to the interface. As the thickness increases to trilayer MoS2, the inner layer is partially shielded from the oxide’s influence, leading to a marginal improvement in mobility, though at the cost of reduced electrostatic control.
Chronology of 2D Material Integration
The publication of this paper represents a milestone in a timeline of research that has spanned more than two decades:
- 2004: Graphene is isolated at the University of Manchester, sparking global interest in 2D materials.
- 2011: The first high-performance MoS2 transistor is demonstrated by researchers at EPFL, showing a high on/off ratio.
- 2015–2018: Research shifts from individual flakes to wafer-scale growth using Chemical Vapor Deposition (CVD). imec begins integrating 2D materials into its pilot line.
- 2021–2023: Industry leaders like TSMC and Intel begin presenting research on 2D channels at major conferences like IEDM, signaling the transition from academic curiosity to industrial roadmap candidate.
- 2024–2025: Intense focus shifts to the "gate stack" problem—finding a way to place high-quality dielectrics on 2D materials without damaging them.
- March 2026: The imec and ETH Zurich study provides a theoretical foundation for understanding oxide-induced degradation, offering a path forward for engineering more resilient interfaces.
Supporting Data and Technical Metrics
The technical paper provides several key data points that illustrate the severity of the degradation. In a "perfect" isolated MoS2 monolayer, theoretical electron mobility can exceed 400 cm²/Vs at room temperature. However, the study shows that when interfaced with amorphous HfO2, the effective mobility can drop by as much as 50% to 70% due to the combined effects of charged impurity scattering and remote phonon scattering.
Furthermore, the research highlights the "Van der Waals gap"—the small physical space between the MoS2 and the oxide. While this gap should theoretically protect the MoS2, the simulations show that the electric fields and the proximity of amorphous atoms still allow for significant electronic coupling. This coupling leads to a "broadening" of the MoS2 energy levels, effectively narrowing the bandgap and increasing the "off-state" leakage current—a critical failure for low-power mobile processors.
Industry Implications and Official Responses
While imec and ETH Zurich function as research entities, their findings have immediate implications for the world’s leading foundries, including TSMC, Samsung, and Intel. These companies are currently developing the architectures that will follow the 2nm node, often referred to as the "A14" or "A10" nodes (referring to Angstrom-scale measurements).
Industry analysts suggest that the results of this study will push the industry toward two possible solutions. First is the development of "buffer layers," such as hexagonal Boron Nitride (hBN), which could act as a pristine 2D insulator between the MoS2 and the amorphous high-k oxide. Second is the exploration of alternative deposition techniques, such as low-temperature Atomic Layer Deposition (ALD), designed to minimize the disruption of the MoS2 lattice during oxide growth.
Inferred reactions from the semiconductor equipment sector suggest that companies like ASML and Applied Materials are closely monitoring this research. The need for "atomically precise" deposition and etching will require new classes of machinery capable of handling 2D materials at a high volume. "The interface is the device," a common mantra in semiconductor engineering, has never been more true than in the context of 2D FETs.
Broader Impact on Global Technology
The successful integration of MoS2 into commercial fabrication lines would represent one of the most significant shifts in material science since the introduction of the transistor. By overcoming oxide-induced degradation, manufacturers could produce chips that are not only faster but also significantly more energy-efficient. This is vital for the continued growth of artificial intelligence (AI), which currently faces massive power consumption challenges in data centers.
Moreover, the findings of Ducry and the team at imec provide a roadmap for academic researchers. By identifying the specific atomic configurations that lead to the worst degradation, the study allows scientists to "screen" new materials and oxide combinations through simulation before moving to expensive and time-consuming laboratory fabrication.
The Path to Commercialization
Despite the challenges outlined in the paper, the outlook for MoS2 remains optimistic. The study does not suggest that MoS2 is unsuitable for transistors; rather, it identifies the specific engineering hurdles that must be cleared. The transition from monolayer to trilayer MoS2, as discussed in the research, may provide a temporary "design window" where performance and reliability are balanced.
As the industry moves toward the late 2020s, the focus will likely shift from "can we build a 2D transistor?" to "can we build a 2D transistor with a lifetime of ten years?" Reliability and degradation studies, such as the one published by imec and ETH Zurich, are the essential building blocks of that transition. The collaboration between these institutions underscores the necessity of a multidisciplinary approach, combining quantum-level physics with industrial-scale engineering to solve the most pressing problems in nanotechnology.
The paper "Oxide induced degradation in MoS2 field-effect transistors" serves as both a warning and a guide for the semiconductor industry. It confirms that the path to the sub-1nm era will not be achieved through simple scaling, but through a fundamental reimagining of how different materials interact at the atomic level. With the theoretical groundwork now laid, the race to implement these findings in a production environment begins in earnest.