The global semiconductor industry is currently navigating a pivotal transition as traditional silicon-based transistors approach their fundamental physical limits. As the industry moves toward the 2nm process node and beyond, the limitations of bulk silicon—specifically regarding short-channel effects and carrier mobility degradation—have necessitated the exploration of alternative materials. Among the most promising candidates are transition metal dichalcogenides (TMDs), a class of two-dimensional (2D) materials that offer the potential to maintain high performance at atomically thin dimensions. While TMDs like molybdenum disulfide (MoS₂) and tungsten diselenide (WSe₂) have transitioned from laboratory curiosities to serious contenders for the next generation of Gate-All-Around (GAA) transistors, a series of formidable integration challenges remains. Recent breakthroughs presented at the IEEE International Electron Devices Meeting (IEDM) suggest that while the path to commercialization is complex, the industry is making significant strides in material growth, contact engineering, and thermal management.
The Physical Imperative for 2D Materials
For decades, the scaling of transistors followed the predictable trajectory of Moore’s Law. However, as silicon channels are thinned to less than five nanometers, the presence of "dangling bonds" at the surface leads to interface scattering. This phenomenon significantly degrades carrier mobility, increasing power consumption and reducing switching speeds. TMDs provide a unique solution to this problem because they are inherently two-dimensional. Their crystal structure consists of a layer of transition metal atoms sandwiched between two layers of chalcogen atoms, held together by strong covalent bonds within the plane.
Crucially, these materials lack out-of-plane dangling bonds. Instead, they interact with adjacent layers through weak van der Waals forces. This lack of surface bonds creates an atomically smooth interface, theoretically allowing for nearly perfect carrier transport even in channels only a few atoms thick. This characteristic makes TMDs ideal for GAA and Complementary Field-Effect Transistor (CFET) architectures, where the gate wraps around the channel to provide maximum electrostatic control.
A Chronology of Integration Challenges
The journey of TMDs began with the mechanical exfoliation of flakes—popularly known as the "Scotch tape method"—which allowed researchers to study the intrinsic properties of these materials but offered no path to mass production. The timeline of progress moved toward Chemical Vapor Deposition (CVD), which enabled the growth of large-area films. However, the requirements for commercial fabrication are far more stringent than those of a research lab.
The primary hurdle has been the high temperatures required for high-quality TMD growth. Conventional CVD processes for MoS₂ often exceed 600°C, a temperature that can damage pre-existing structures on a silicon wafer, such as dielectrics and metal interconnects. Furthermore, the lack of surface bonds, while beneficial for mobility, makes it extremely difficult for TMDs to adhere to substrates. This poor adhesion often leads to delamination during the rigorous chemical and mechanical polishing steps required in modern fab environments.
Breakthroughs in Material Fabrication and Direct Growth
To address the scalability issue, researchers are shifting away from "transfer" methods—where the TMD is grown on a sacrificial substrate like sapphire and moved to silicon—and toward direct growth. At the most recent IEDM, Samsung researchers presented a significant advancement in this area. By depositing a thin passivating oxide atop MoS₂ channels, the team was able to shield the 2D material from the harsh plasma environments of subsequent processing steps.
Samsung’s group also utilized a selective oxidation technique. By allowing oxygen to diffuse through a thin oxide layer, they selectively oxidized the edges of the TMD channel. These oxidized regions formed strong chemical bonds with the underlying substrate, effectively "anchoring" the 2D film and preventing the delamination that has long plagued the technology. This method also demonstrated a reduced thermal budget, making it more compatible with existing CMOS manufacturing flows.
Simultaneously, a collaboration between CEA-Leti and Intel showcased a "channel-last" integration scheme. This approach is strategically designed to preserve as much of the standard silicon GAA process as possible. In this workflow, a Si/SiGe multilayer stack is processed through the replacement metal gate steps. Only then are the sacrificial layers removed and replaced with MoS₂ for n-type transistors and WSe₂ for p-type transistors via Atomic Layer Deposition (ALD). This methodology represents a pragmatic middle ground, allowing fabs to leverage existing infrastructure while introducing 2D materials at the final stages of device formation.
Solving the Contact and Dielectric Interface Crisis
Even when a high-quality TMD film is successfully deposited, the device’s performance is often throttled by the interface between the semiconductor and the metal contacts. Because TMDs are atomically thin, they are highly sensitive to "Fermi-level pinning," a phenomenon where the energy levels at the metal-semiconductor interface become fixed, leading to high contact resistance.
TSMC researchers have identified that the gap between theoretical and actual performance is widest in p-type TMD devices. Their investigation into Pd/WSe₂ contacts revealed that selenium vacancies at the interface were a primary culprit for poor performance. By occupying these vacancies with phosphorus dopants, the TSMC team was able to lower contact resistance significantly. This type of substitutional doping is viewed as a "robust and flexible" solution compared to simply searching for metals with higher work functions.
In tandem, imec has focused on the dielectric stack. The challenge lies in depositing a high-k dielectric, such as hafnium oxide (HfO₂), onto a surface that has no bonds to latch onto. Imec’s solution involved using an aluminum oxide (Al₂O₃) buffer layer. This layer serves a dual purpose: it acts as an adhesion seed for the HfO₂ and protects the MoS₂ channel from damage during deposition. Through a selective etching technique, they were able to remove the Al₂O₃ from specific areas of the gate stack, allowing for more precise control over the device’s electrical characteristics.
Toward Complementary Logic and Heterogeneous Stacking
The ultimate goal of 2D semiconductor research is the creation of a complete logic ecosystem. This requires both n-type (electron-carrying) and p-type (hole-carrying) transistors. While MoS₂ is an excellent n-type material, WSe₂ has emerged as the frontrunner for p-type applications. However, integrating two different TMDs on the same wafer remains a manufacturing nightmare.
Fudan University researchers recently bypassed this complexity by demonstrating a microprocessor built entirely on MoS₂. By using different gate metals (aluminum and gold) to create both enhancement-mode and depletion-mode devices, they fabricated a functional microprocessor containing nearly 6,000 transistors. While this "all-n-type" logic is less power-efficient than true CMOS, the demonstration of such high-density integration on a sapphire substrate marks a major milestone for 2D material maturity.
For true CMOS performance, other groups are looking at vertical stacking. Fudan University also demonstrated a hybrid CFET (Complementary Field-Effect Transistor) by stacking n-type MoS₂ transistors directly on top of p-type Silicon-on-Insulator (SOI) devices. This heterogeneous approach, combining the best of the old world with the new, outperformed pure silicon CFETs in terms of gain and power consumption, suggesting that the first commercial 2D devices might be "hybrids" rather than pure 2D systems.
Thermal Management: The Hidden Bottleneck
As the industry moves closer to functional 2D devices, a new concern has emerged: heat. Silicon is a relatively good conductor of heat, but TMDs possess very poor out-of-plane thermal conductivity. Furthermore, the high-k dielectrics used to gate these devices are also poor thermal conductors.
Research from Stanford University indicates that heat dissipation in 2D transistors will occur almost exclusively through the metallic contacts and circuit wiring. In simulations, TMD devices experienced a temperature rise three times higher than that of silicon counterparts under similar loads. Stanford researchers found that "wrap-around" contacts—which increase the surface area between the metal and the 2D channel—offered better cooling than traditional edge contacts. They also experimented with intercalating lithium into multilayer TMDs, which improved thermal performance to within 50% of silicon standards. Without solving these thermal "hot spots," the reliability of 2D chips would be compromised, regardless of their electrical performance.
Analysis of Broader Industry Implications
The transition to 2D semiconductors represents more than just a material change; it is a fundamental shift in the semiconductor supply chain. If TMDs become the standard, the demand for specialized ALD and CVD equipment will surge, while traditional silicon ingot growth and wafer slicing might see a relative decline in importance for the leading edge.
Furthermore, the geopolitical stakes are high. With research hubs in the United States (Intel, Stanford, Purdue), Europe (imec, CEA-Leti), and Asia (Samsung, TSMC, Fudan), the race for 2D supremacy is global. The first company or nation to successfully stabilize the manufacturing of 2D CFETs will likely dominate the high-performance computing and mobile processor markets for the next two decades.
In conclusion, transition metal dichalcogenides have evolved from laboratory novelties into the most viable successors to silicon. The recent findings from IEDM highlight a shift in focus from "can we make these devices work?" to "can we make these devices at scale?" While the hurdles of adhesion, contact resistance, and thermal management are significant, the coordinated efforts of the world’s leading foundries and research institutes suggest that the 2D era of computing is no longer a matter of "if," but "when." The path forward will likely involve a gradual introduction of TMDs into silicon flows, eventually leading to a paradigm shift in how we build the brains of our digital world.