The semiconductor industry is currently navigating a pivotal transition as traditional planar scaling reaches its physical and economic limits. As global demand for high-performance computing, artificial intelligence, and energy-efficient mobile devices continues to surge, the fabrication of integrated circuits has moved into the realm of three-dimensional (3D) architectures. This shift has necessitated a fundamental evolution in manufacturing techniques, moving away from bulk processing toward atomic-scale precision. A comprehensive review recently published by a multinational coalition of researchers highlights the critical advancements in plasma processing that are enabling this next generation of microelectronics.
The technical paper, titled "Recent Progress in Atomic-Scale Controlled Plasma Processing," represents a collaborative effort between Nagoya University, Boise State University, the Korea Institute of Fusion Energy, Hitachi High-Tech Corporation, and the Princeton Plasma Physics Laboratory (PPPL). Published in the June 2026 issue of the Japanese Journal of Applied Physics, the review outlines the state-of-the-art methodologies required to manipulate matter at the level of individual atoms, a prerequisite for the mass production of Gate-All-Around (GAA) transistors, Complementary FETs (CFETs), and advanced 3D NAND memory structures.
The Evolution of Plasma Processing in Semiconductor Fabrication
Since the inception of the integrated circuit, plasma-based etching and deposition have been the workhorses of the cleanroom. Plasma, often referred to as the fourth state of matter, provides the reactive ions and radicals necessary to carve intricate patterns into silicon wafers. However, as feature sizes have shrunk below the 5-nanometer (nm) node, traditional continuous-wave plasma etching has faced significant hurdles.
In the past, the primary goal of plasma processing was throughput and macro-scale uniformity. Today, the focus has shifted to "atomic-scale control." This involves the ability to remove or add a single monolayer of material without damaging the underlying lattice or compromising the structural integrity of neighboring features. The transition from bulk processing to atomic layer processing is not merely a refinement of existing techniques but a paradigm shift in how plasma-surface interactions are managed.
The chronology of this development began with the introduction of Atomic Layer Deposition (ALD) in the late 20th century, which allowed for the conformal growth of thin films. However, the "etch" side of the equation—Atomic Layer Etching (ALE)—remained a laboratory curiosity for decades. It was only with the advent of extreme ultraviolet (EUV) lithography and the requirement for high-aspect-ratio (HAR) features that ALE became an industrial necessity. The new research highlights how ALE has now reached a level of maturity where it can be integrated into high-volume manufacturing (HVM) environments.
Technical Breakthroughs in Atomic Layer Etching (ALE)
The core of the recent progress documented by the research team involves the refinement of the ALE cycle. Unlike traditional etching, which uses a continuous stream of plasma, ALE operates through sequential, self-limiting reactions. The process typically involves two stages: a modification step, where the surface of the material is chemically altered to a specific depth, and a removal step, where only the modified layer is etched away using low-energy ion bombardment.
One of the primary challenges addressed in the review is the management of the "plasma sheath"—the boundary layer between the bulk plasma and the wafer surface. By controlling the energy distribution of ions hitting the surface, researchers have demonstrated the ability to etch features with aspect ratios exceeding 100:1. This is particularly vital for 3D NAND flash memory, where deep holes must be drilled through hundreds of layers of alternating materials with perfect verticality.
Supporting data provided in the review indicates that modern atomic-scale plasma processes can achieve selectivity ratios previously thought impossible. For instance, the ability to etch silicon nitride while leaving silicon dioxide untouched is a critical requirement for the fabrication of "spacer" structures in advanced transistors. The researchers report that by utilizing pulsed-power plasma sources and advanced fluorocarbon chemistries, selectivity can be maintained even at the sub-2nm scale.
The Role of High-Aspect-Ratio (HAR) Structures and 3D Architectures
As the industry moves toward 3D integration, the geometry of devices becomes increasingly complex. In a traditional planar transistor, the gate sits on top of a channel. In a FinFET, it wraps around three sides. In the latest GAAFET (Gate-All-Around) designs, the gate completely surrounds the channel, which often consists of multiple "nanosheets."
Fabricating these nanosheets requires the selective removal of sacrificial layers (typically silicon-germanium) from between silicon layers. This "lateral etching" must be controlled with atomic precision to ensure that the silicon channel remains undamaged. The review by Ishikawa et al. emphasizes that atomic-scale plasma processing is the only viable method for achieving the necessary uniformity across a 300mm wafer.
Furthermore, the research highlights the emergence of High-Aspect-Ratio (HAR) challenges in DRAM (Dynamic Random Access Memory). As capacitors are stretched vertically to save horizontal space, they become prone to "tilting" or "bowing" during the etching process. The international team presented data showing how synchronized pulsing of the plasma source and the wafer bias can mitigate these effects, ensuring that features remain perfectly upright and uniform from top to bottom.
Institutional Collaboration and the Global Research Landscape
The diversity of the institutions involved in this research reflects the global nature of the semiconductor supply chain. Nagoya University and Hitachi High-Tech Corp represent the strong link between Japanese academic research and industrial equipment manufacturing. Hitachi, a leader in plasma etching systems, provides the hardware platforms that translate theoretical plasma physics into repeatable industrial processes.
The inclusion of the Korea Institute of Fusion Energy and the Princeton Plasma Physics Laboratory (PPPL) underscores the importance of fundamental plasma science. PPPL, traditionally focused on nuclear fusion, has increasingly applied its expertise in plasma diagnostics and modeling to the microelectronics field. Their contribution involves sophisticated computer simulations that track the trajectory of individual ions and radicals within the plasma, allowing engineers to predict how different gas mixtures will behave in a reactor.
Boise State University, located near the headquarters of Micron Technology, brings a focus on memory applications and material science. This collaborative ecosystem allows for a feedback loop where fundamental physics informs tool design, which is then validated through material analysis and electrical testing.
Industry Implications and Economic Impact
The implications of atomic-scale controlled plasma processing extend far beyond the laboratory. The semiconductor industry is currently a $600 billion global market, expected to reach $1 trillion by 2030. The ability to master these advanced etching and deposition techniques is a key differentiator for leading edge-foundries like TSMC, Samsung, and Intel.
From an economic perspective, the shift to atomic-scale control is a response to the rising costs of fabrication. As the complexity of chips increases, the margin for error shrinks. A single atomic defect can render a multi-billion-transistor chip useless. By implementing self-limiting processes like ALE, manufacturers can significantly improve "yield"—the percentage of working chips on a wafer. High yield is the primary driver of profitability in the semiconductor sector.
Moreover, the review touches upon the environmental and sustainability aspects of plasma processing. Traditional etching often uses high-global-warming-potential (GWP) gases. The research team highlights new "green" chemistries and more efficient plasma generation methods that reduce the environmental footprint of the fabrication process while maintaining atomic-level precision.
Future Outlook: Toward the 1-Nanometer Node and Beyond
Looking ahead, the review identifies several "grand challenges" that the industry must overcome to reach the 1nm node. One such challenge is the integration of new materials, such as two-dimensional (2D) semiconductors like molybdenum disulfide (MoS2). These materials are only one or two atoms thick, making traditional processing techniques obsolete.
The researchers argue that the future of the industry lies in "Area-Selective Processing." This involves using plasma to treat specific areas of a wafer so that subsequent deposition or etching occurs only where intended, without the need for traditional lithographic masking. This would represent the ultimate realization of atomic-scale control, where chips are built atom-by-atom in a bottom-up fashion rather than the top-down subtractive methods used today.
In the near term, the techniques described in "Recent Progress in Atomic-Scale Controlled Plasma Processing" will be instrumental in the rollout of the next generation of AI hardware. The massive parallel processing required for large language models (LLMs) demands chips with unprecedented transistor density and interconnect bandwidth. The atomic-scale precision enabled by this research is the foundation upon which these future computing systems will be built.
As the industry moves toward the late 2020s, the synergy between plasma physics, material science, and precision engineering will remain the primary engine of Moore’s Law. The work of Kenji Ishikawa and his colleagues serves as both a summary of current achievements and a roadmap for the future of nano-fabrication, ensuring that the limits of silicon can be pushed for at least another decade of innovation.
