The landscape of semiconductor design is undergoing a fundamental shift as artificial intelligence integrates into the creation and utilization of architectural and behavioral models. In the high-stakes world of Electronic Design Automation (EDA), a model is defined as a representation that captures specific behaviors exhibited in the real world. However, the industry has long operated under the axiom that all models are compromises; they intentionally sacrifice granular detail to achieve the execution performance necessary for modern compute-intensive workloads. As chip complexity scales toward trillion-transistor systems, the traditional methods of manual model creation are being augmented—and in some cases replaced—by AI-driven surrogate models, reinforcement learning loops, and large language models (LLMs).
The hierarchy of modeling begins with the design itself, followed by a suite of verification models that ensure the hardware will function as intended. These models exist across a spectrum of abstraction. At the base, physics-based transistor models provide high fidelity but are computationally expensive. Above these sit gate-level and arithmetic models, which are further abstracted into Register Transfer Level (RTL) models—the clock-accurate standard for digital design. Each layer of this hierarchy serves a specific purpose, provided it is not utilized outside the context for which it was originally characterized. The introduction of AI into this flow promises to accelerate the creation of these models, but it also introduces significant questions regarding accuracy, traceability, and the fundamental nature of verification trust.
The Evolution of Abstraction and the Role of Surrogate Models
The primary motivation for creating surrogate models is speed. In the analog and mixed-signal domains, running full SPICE (Simulation Program with Integrated Circuit Emphasis) or electromagnetic (EM) simulations across every possible corner and stimulus is often prohibitive in terms of time and cost. Surrogate models act as approximations, capturing the essential behavior of a circuit while ignoring non-essential details. This allow designers to run thousands of iterations in the time it would previously have taken to run one.
AI is now being leveraged to automate the generation of these surrogates. Tools such as Synopsys’s DSO.ai and Cadence’s Cerebrus utilize reinforcement learning to create optimization loops for block-based physical implementation. These tools analyze the Power, Performance, and Area (PPA) results of each trial, feeding the data back into the AI model to inform more efficient tool settings for subsequent iterations. While these implementation tools work with relatively stable RTL design models, the industry is now turning its attention to more volatile areas of the flow, specifically verification.
In verification, the goal is to identify errors in either the design or the testbench as early as possible. This is a convergence process where the target—the design under test—is often moving as bugs are fixed and features are added. Arvind Srinivasan, product engineering lead for Normal Computing, notes that measuring accuracy in this context is challenging because ground truth simulations are expensive. Srinivasan suggests that the industry faces a choice: either learn physical rules that generalize (which is computationally complex) or use "world models" and LLMs to transfer semantic knowledge, bypassing explicit physical constraints.
A Framework for AI-Driven Model Creation
To understand how AI is reshaping the workflow, industry experts point to a structured six-step process for model generation. This classical approach, adapted for the AI era, emphasizes that model creation is not a one-shot event but an iterative cycle:
- Specification Analysis: The process begins with analyzing the design specification, timing diagrams, and requirements to establish a mental model of the intended behavior.
- Data Acquisition: High-fidelity "golden" simulations or historical regression data are collected to serve as the training set.
- Parameter Extraction: AI agents analyze the data to extract key parameters and identify the boundaries of the model’s application.
- Model Synthesis: An initial behavioral model (often in Verilog-A or SystemVerilog) is generated.
- Validation and Gap Detection: The AI-generated model is compared against the golden reference to identify deviations.
- Iterative Refinement: If the accuracy is insufficient, the agent intelligently selects new simulation points to maximize information gain and recreates the model.
This process highlights the necessity of "active learning." Rather than running a predefined grid of simulations, AI agents can identify where model uncertainty is highest and trigger specific simulations to fill those gaps. This reduces the manual burden on engineers while ensuring the resulting model is fit for its intended purpose.
The Dual Axes of Reliability: Accuracy vs. Completeness
One of the most critical distinctions in the modeling discourse is the difference between accuracy and completeness. Ashish Darbari, CEO of Axiomise, argues that while accuracy is about how closely a model’s predictions match trusted outcomes, completeness is a measure of coverage. A model may be highly accurate in common scenarios but fail to account for rare protocol interactions, reset behaviors, or low-power modes.
In the analog space, Hanna Yip of Normal Computing describes accuracy as a statistical distribution question: how close are the outputs to the ground truth? Completeness, conversely, asks if the model has defined behavior for all relevant scenarios. A model that is "silently wrong" on rare corner cases can lead to catastrophic silicon failures, even if it performs perfectly in 99% of nominal simulations. This is particularly relevant in DRAM verification, where failure modes like timing violations are systematically underrepresented in typical simulation traces.
To mitigate these risks, the industry is looking toward more compact representations. Thomas Ahle, head of machine learning at Normal Computing, points to recent advancements in weather modeling where "bottleneck layers" force models to discover fundamental physical laws rather than memorizing millions of specific rules. By forcing AI to find the most compact way of representing a system, engineers can increase the likelihood that the model will generalize to unseen data.
Validation, Tagging, and the Necessity of Trust
The adoption of AI-generated models is currently tethered to the ability of engineering teams to trust the output. A common pitfall in the current era is "hallucination," where an AI model produces a plausible but factually incorrect representation. To combat this, experts suggest a "hybrid" approach to validation. Tom Demuer of Keysight EDA recommends a ratio-based verification strategy: for every 50 evaluations of an AI model, one evaluation is performed against the true ground truth to ensure the surrogate remains within acceptable bounds.
Furthermore, the concept of "tagging" or metadata attachment has become essential. Every AI-generated model must be labeled with its intended scope, its parameter range, and its "pedigree." This includes watermarking AI-generated content to distinguish it from human-authored code. Sathishkumar Balasubramanian, head of products at Siemens EDA, emphasizes that data labeling and authentication must begin at the source. Without a disciplined process to validate the data used for fine-tuning, the resulting models cannot be used in safety-critical designs.
Simon Davidmann, an AI and EDA researcher at the University of Southampton, warns that current benchmarks like VerilogEval are insufficient for industrial-scale SoC (System on Chip) complexity. These benchmarks often focus on short, pedagogical modules. A model that scores 90% on a standard benchmark may still fail when confronted with a complex cache controller or non-trivial Clock Domain Crossing (CDC) handling. Davidmann argues that the industry needs a "deliberate boundary-probing exercise" to identify where a model’s certainty ends and its risks begin.
Industry Implications and the Path Forward
The implications of AI-driven modeling extend beyond mere productivity gains. If successfully implemented, these models can dramatically reduce the cost of design re-spins, which for advanced nodes can reach tens of millions of dollars. However, the shift requires a cultural change within engineering teams. AI models in verification are currently viewed as "advisory" rather than "sign-off" engines. They can recommend which tests to run or suggest assertions, but they are not yet permitted to declare verification closure independently.
The consensus among EDA leaders is that the future of modeling will be defined by traceability and human-in-the-loop oversight. Agents can reduce the burden of gap detection and automated test generation, but human engineers must remain the final authority on sign-off evidence. As AI continues to evolve, the distinction between human-authored and AI-generated content will become a standard part of documentation, particularly for industries like automotive and aerospace where functional safety is paramount.
Ultimately, the transformation of semiconductor modeling through AI is a balance between the pursuit of speed and the requirement for absolute correctness. While AI can process vast amounts of data and identify patterns invisible to the human eye, it lacks the innate understanding of physical constraints that a domain expert possesses. The industry’s path forward lies in combining the computational power of AI with the rigorous, rule-based verification methods that have defined semiconductor excellence for decades. Only through this synthesis can the potential of AI be fully realized without compromising the integrity of the world’s most complex silicon designs.
