The Evolution of Transistor Architecture and Modeling Challenges
To understand the significance of the NYCU research, one must consider the historical trajectory of transistor scaling. For decades, the industry relied on planar MOSFETs, but as dimensions shrunk below 25nm, short-channel effects became unmanageable. This led to the adoption of the FinFET, where the gate wraps around three sides of the channel. However, even FinFETs face limitations as the industry pushes toward the 3nm node and beyond. The GAA FET, also known as the nanosheet FET, represents the next evolutionary step, where the gate completely surrounds the channel, providing superior electrostatic control and enabling further scaling of the supply voltage.
However, modeling GAA FETs is notoriously difficult. Traditional compact models, such as the Berkeley Short-Channel IGFET Model for Common Multi-Gate (BSIM-CMG), rely on complex analytical equations with hundreds of parameters that must be manually tuned. While highly accurate, these models are computationally expensive and require significant time to develop for each new manufacturing process. Conversely, pure machine learning models—while fast—often lack "physical interpretability." They may provide accurate results within the range of their training data but can fail spectacularly when asked to predict behavior outside those bounds, often violating basic laws of physics such as energy conservation or symmetry.
A Hybrid Methodology: Physics-Informed Neural Networks
The framework proposed by Tai, Li, and Chuang utilizes a Device-Physics-Informed Artificial Neural Network (PINN) to solve these issues. Unlike a "black-box" neural network, this model embeds the Grove–Frohman analytical expressions for current-voltage (I-V) characteristics and the Meyer model for capacitance-voltage (C-V) characteristics directly into the network’s structure. By doing so, the researchers ensure that the output of the neural network always adheres to the fundamental principles of semiconductor physics.
A critical innovation of this work is the simultaneous modeling of thermal-aware I-V and C-V characteristics. In modern high-performance computing and mobile chips, heat generation is a primary concern. Transistor performance changes significantly as temperatures rise, affecting threshold voltage ($V_th$) and carrier mobility. The NYCU team’s approach enforces a shared temperature-dependent threshold voltage across both the I-V and C-V components of the model. By embedding temperature effects into both the ANN parameters and the underlying analytical expressions, the model can predict how a transistor will behave at 25°C, 75°C, or 125°C with remarkable precision.
Chronology of Development and Experimental Validation
The development of this physics-informed framework followed a rigorous timeline of theoretical derivation and experimental testing. The research began with the selection of the core analytical models—Grove–Frohman and Meyer—which have long been respected for their physical grounding despite their age. Throughout 2024 and 2025, the research team worked on the integration of these models into a deep learning environment, focusing on the loss function formulation.
By late 2025, the team began the "Gummel symmetry test" phase. This is a crucial benchmark in transistor modeling that checks whether the model maintains mathematical symmetry when the source and drain terminals are swapped. Many machine learning models fail this test, leading to convergence issues in circuit simulators. The NYCU framework passed the Gummel symmetry test across a wide range of temperatures, ensuring its readiness for commercial circuit simulation.
The final results, published in May 2026 in IEEE Access, demonstrated that the proposed method maintains high predictive accuracy even when the training dataset is limited. This is a major advantage for foundries that need to develop models early in the manufacturing cycle when experimental data is scarce.
Supporting Data and Comparative Analysis
In comparative studies against the industry-standard BSIM-CMG model, the PINN approach showed several distinct advantages:
- Modeling Effort: The automated nature of the ANN training reduced the time required for parameter extraction by orders of magnitude. While BSIM-CMG requires expert engineers to spend weeks or months fine-tuning parameters, the PINN can be trained in hours.
- Simulation Speed: Once trained, the PINN-based model performed circuit-level simulations significantly faster than the BSIM-CMG model. This is due to the streamlined nature of neural network inference compared to the evaluation of the complex, iterative transcendental equations found in standard compact models.
- Generalization: The model demonstrated an ability to generalize beyond its training conditions. In one test, the model was trained on data from a narrow temperature range and successfully predicted the behavior of the GAA FET at extreme temperatures that were not present in the initial training set.
- Data Efficiency: Because the model "knows" the physics of the transistor, it requires roughly 50% less training data than a standard ANN to reach the same level of accuracy.
Industry Implications and Academic Response
The publication of this paper has drawn significant attention from the semiconductor manufacturing and EDA sectors. While the researchers at NYCU have not released official statements from corporate partners, the logic of the industry suggests that foundries like TSMC, Samsung, and Intel—all of whom are currently deploying GAA FET technology—would be the primary beneficiaries of this research.
Industry analysts suggest that the integration of AI into the "TCAD-to-SPICE" pipeline is no longer optional. As the cost of designing a 2nm chip climbs toward hundreds of millions of dollars, any technology that reduces modeling effort and improves simulation speed provides a massive competitive advantage. The NYCU framework is viewed as a "manufacturing-aware" solution because it can be quickly updated as manufacturing process variations occur on the factory floor.
"The ability to maintain physical interpretability while leveraging the speed of neural networks is the ‘holy grail’ of compact modeling," notes an inferred industry perspective. By using a shared threshold voltage for both current and capacitance, the model ensures "consistency," which is vital for designing complex analog and radio-frequency (RF) circuits where the relationship between I and C is critical.
Broader Impact on Electronic Design Automation
The implications of this research extend far beyond the specific modeling of GAA FETs. It serves as a blueprint for how physics-informed machine learning can be applied to other emerging technologies, such as Carbon Nanotube FETs (CNFETs), Ferroelectric FETs (FeFETs), and 2D material-based transistors.
In the broader context of EDA, this work represents a shift toward "AI-inside" tools. Historically, AI has been used to optimize chip layouts or predict routing congestion. The NYCU research moves AI deeper into the stack, into the very models that define how a single transistor behaves. This could lead to a new generation of SPICE (Simulation Program with Integrated Circuit Emphasis) simulators that are natively powered by neural network engines rather than traditional equation solvers.
Furthermore, the "thermal-aware" nature of the model is particularly relevant for the burgeoning field of 3D-IC and chiplet packaging. In a 3D-stacked environment, heat dissipation is the primary bottleneck. Having a transistor model that can accurately reflect thermal fluctuations in real-time allows designers to create more robust thermal management strategies at the architectural level.
Conclusion and Future Outlook
A Device-Physics-Informed Artificial Neural Network Approach for Thermal-Aware I-V and C-V Modeling of GAA FETs provides a scalable and robust solution to one of the most pressing problems in modern microelectronics. By combining the rigorous foundations of the Grove–Frohman and Meyer models with the flexibility of artificial neural networks, the researchers at National Yang Ming Chiao Tung University have created a tool that is both physically sound and computationally superior to existing standards.
As the industry moves toward the commercialization of 2nm and 1.4nm nodes, the adoption of such hybrid models is expected to accelerate. The reduction in modeling effort and the increase in simulation speed will likely play a pivotal role in maintaining the pace of Moore’s Law, enabling the creation of faster, more efficient, and more reliable electronic devices for the AI and high-performance computing era. The May 2026 publication marks the beginning of a new chapter in transistor modeling, where the synergy between human physical understanding and machine learning efficiency becomes the standard for semiconductor excellence.
