As the semiconductor industry pushes beyond the physical limits of traditional silicon architectures, researchers from San Jose State University (SJSU) and Sandia National Laboratories have released a comprehensive technical study focusing on the critical challenges of thermal management and atmospheric radiation in next-generation 3-nanometer (nm) Gate-All-Around Field-Effect Transistor (GAA-FET) technology. The research, published in July 2026, investigates the performance of Static Random-Access Memory (SRAM) cells—the backbone of modern cache memory—under the extreme scaling requirements of the 3nm node. By evaluating various substrate isolation techniques, the study provides a roadmap for enhancing the reliability of high-performance computing (HPC) and aerospace electronics.
The transition from FinFET (Fin Field-Effect Transistor) to GAA-FET (also known as nanosheet transistors) represents one of the most significant architectural shifts in microelectronics history. While FinFETs dominated the industry from the 22nm to the 5nm nodes, the move to 3nm and below necessitated a structure where the gate surrounds the channel on all sides to maintain electrostatic control and minimize leakage. However, this increased density brings two primary "silent killers" of chip reliability: self-heating effects (SHE) and radiation-induced Single Event Upsets (SEUs). The collaborative paper by Albert Lu, Junipero Verbeke, Phil Oldiges, Reza Arghavani, and Hiu Yung Wong addresses these issues by proposing and simulating novel isolation structures that balance thermal dissipation with radiation hardness.
The Evolution of Substrate Isolation in GAA-FETs
In traditional semiconductor manufacturing, the isolation of the transistor from the underlying silicon substrate is paramount to preventing current leakage and parasitic capacitance. In the FinFET era, this was often managed through doping profiles known as Punch-Through Stoppers (PTS). However, as the industry enters the 3nm GAA-FET era, PTS has proven insufficient for the rigorous demands of low-power, high-frequency operation.
The research highlights three distinct approaches to substrate isolation:
- Punch-Through Stopper (PTS): The baseline technique that uses heavy doping under the channel to prevent sub-surface leakage. While easy to integrate, it offers the least protection against thermal build-up and radiation-induced charge collection.
- Source/Drain Bottom Dielectric Isolation (SD-BDI): This technique involves placing a dielectric layer (usually silicon dioxide or a low-k material) directly beneath the source and drain regions. This effectively cuts off the path for leakage current to the substrate and significantly reduces parasitic capacitance, which boosts switching speeds.
- Channel-Bottom Dielectric Isolation (C-BDI): A novel proposal by the SJSU and Sandia team. Unlike SD-BDI, which isolates the entire active area, C-BDI places the dielectric isolation specifically under the channel while allowing a direct connection between the source/drain (S/D) regions and the substrate. This "hybrid" approach aims to solve the thermal bottleneck associated with GAA-FETs.
Addressing the Thermal Bottleneck: Self-Heating Effects
One of the primary findings of the study is the quantifiable impact of isolation on Self-Heating Effects (SHE). In a GAA-FET, the channel consists of multiple stacked nanosheets. Because these sheets are surrounded by gate dielectrics and spacers—materials with low thermal conductivity—the heat generated during transistor operation becomes trapped. This leads to a localized temperature rise that can degrade carrier mobility, reduce reliability through electromigration, and accelerate aging mechanisms like Bias Temperature Instability (BTI).
The researchers utilized advanced Technology Computer-Aided Design (TCAD) simulations to model the thermal profile of a 3nm SRAM cell. The data revealed that while standard SD-BDI provides excellent electrical isolation, it acts as a thermal insulator, trapping heat within the nanosheet stack. By contrast, the proposed C-BDI structure leverages the source and drain regions as "heat sinks." By allowing a physical and thermal connection from the S/D to the substrate, the C-BDI architecture provides a low-resistance path for heat to dissipate into the bulk silicon. This finding suggests that C-BDI could be essential for AI processors and server CPUs that operate at high duty cycles where thermal throttling is a constant concern.
Radiation Hardness and Single Event Upsets
Beyond thermal management, the paper provides a rigorous analysis of radiation hardness, a field of particular interest to Sandia National Laboratories given their mandate for national security and aerospace reliability. At the 3nm node, the "critical charge" ($Q_crit$)—the minimum amount of charge required to flip the state of a memory bit—is incredibly small. This makes SRAM cells highly susceptible to Single Event Upsets (SEUs) caused by alpha particles from chip packaging materials or cosmic rays.
The study’s findings on radiation are particularly promising for the future of "rad-hard" electronics:
- Alpha-Particle Immunity: The researchers report that at the 3nm node, the GAA-FET SRAM structures demonstrate a high degree of natural immunity to alpha-particle-induced SEUs compared to previous planar generations. This is largely due to the reduced volume of the active silicon area, which presents a smaller target for particle strikes.
- BDI Enhancement: The implementation of Bottom Dielectric Isolation (both SD-BDI and C-BDI) was found to enhance radiation hardness "substantially." By physically separating the active device from the substrate, the dielectric layer prevents charges generated deep in the silicon by a radiation strike from being collected by the transistor terminals.
The paper concludes that BDI structures effectively "decouple" the substrate from the sensitive nodes of the SRAM cell. This is a critical discovery for satellite manufacturers and defense contractors, as it suggests that the same techniques used to improve performance in consumer electronics can also be leveraged to create more resilient hardware for space and high-altitude environments.
Chronology of Research and Development
The timeline leading to this publication reflects the broader industry’s struggle to maintain Moore’s Law.
- 2022-2023: Major foundries like Samsung and TSMC began the rollout of early-stage 3nm processes. Initial reports focused heavily on yield and basic power-performance-area (PPA) metrics.
- 2024-2025: As the first 3nm chips entered the market, secondary effects such as SHE and reliability in extreme environments became the primary focus of academic and industrial research.
- Late 2025: The collaboration between SJSU and Sandia National Laboratories was established to specifically address the intersection of thermal physics and radiation effects in GAA-FETs, recognizing that these two factors are often at odds (materials that block radiation often trap heat).
- July 2026: The publication of "Self-Heating and Radiation Hardness Studies of 3nm GAA-FET-Based SRAM" provides the first comprehensive comparison of C-BDI and SD-BDI in a 3nm context.
Industry Implications and Expert Analysis
The implications of this study reach far beyond the laboratory. For semiconductor foundries, the choice between PTS, SD-BDI, and the newly proposed C-BDI will define the competitive landscape of the late 2020s.
Industry analysts suggest that the adoption of C-BDI could be a "game-changer" for mobile processors. In a smartphone, where there are no active cooling fans, the ability of the SRAM cache to dump heat into the substrate could allow for longer bursts of high-performance operation without thermal throttling. Furthermore, as the industry moves toward 2nm and 1.4nm nodes (often referred to as the "Angstrom era"), the thermal and radiation challenges identified by Lu et al. will only intensify.
The involvement of Sandia National Laboratories also signals a shift in how the U.S. government views commercial semiconductor advancements. By studying the radiation hardness of "off-the-shelf" 3nm architectures, the research supports the "Prototyping to Production" pipeline, ensuring that the most advanced commercial nodes can be hardened for use in critical infrastructure and defense systems without requiring entirely separate, legacy manufacturing processes.
Technical Data and Simulation Parameters
To ensure the validity of their findings, the research team employed a 3D-TCAD framework that accounted for:
- Quantization Effects: Using the Density Gradient model to account for the quantum nature of electrons in 3nm-thin nanosheets.
- Thermal Conductivity Scaling: Adjusting the thermal conductivity of silicon, as it drops significantly when dimensions are smaller than the phonon mean free path.
- Charge Collection Models: Simulating heavy-ion and alpha-particle strikes at various angles and energies to map the "sensitive volume" of the SRAM cell.
The data showed that SD-BDI reduced the peak temperature of the nanosheets by approximately 5-10% compared to a non-isolated structure, but C-BDI outperformed both by providing a 15-20% improvement in heat dissipation while maintaining identical radiation hardness benefits to SD-BDI.
Conclusion and Future Outlook
The paper titled "Self-Heating and Radiation Hardness Studies of 3nm GAA-FET-Based SRAM with Different Substrate Isolation Techniques" serves as a pivotal reference for the next five years of semiconductor development. As the industry prepares for the mass production of 2nm devices, the lessons learned here regarding Bottom Dielectric Isolation will likely become standard practice.
The research proves that the move to GAA-FETs is not merely a change in shape, but a fundamental shift in how engineers must approach the physics of heat and radiation. By proposing C-BDI, the team from San Jose State University and Sandia National Laboratories has offered a rare "win-win" solution in the world of engineering: a technique that improves thermal reliability without compromising the chip’s ability to withstand the harsh radiation environment of our atmosphere and beyond.
As high-performance computing continues to demand more transistors in smaller spaces, the balance between isolation and dissipation will remain the central challenge of the silicon frontier. This study ensures that as we shrink the dimensions of our technology, we do not sacrifice the stability and durability that modern civilization relies upon.
