The semiconductor industry is currently navigating a period of unprecedented architectural transformation, shifting from traditional FinFET designs to advanced nanosheet and stacked-transistor configurations. A recent collaborative research effort involving the Technical University of Munich (TUM), the University of Modena and Reggio Emilia, and Applied Materials has provided critical insights into this transition. Their technical paper, released in September 2026, introduces a sophisticated System-Technology Co-Evaluation (STCO) flow designed to bridge the gap between microscopic device physics and macroscopic chip-level performance, specifically comparing the A10 Nanosheet FET (NSFET) node with the emerging A7 Complementary FET (CFET) architecture.
The Shift Toward Vertical Integration
For over a decade, FinFETs served as the workhorse of the industry, but as scaling reached the sub-5nm regime, the limits of 3D-gate control became apparent. The industry transitioned toward Nanosheet FETs (NSFETs) or Gate-All-Around (GAA) architectures, which provide superior electrostatic control. However, as the industry looks toward the 1nm (A10) and sub-1nm (A7) horizons, the footprint of standard cells remains a bottleneck.
The CFET architecture represents the next frontier. By stacking n-type and p-type devices vertically rather than placing them side-by-side, CFETs offer a path to significantly higher transistor density and improved power efficiency. Yet, this vertical integration introduces complex parasitic resistance and capacitance (RC) challenges, as well as new thermal dissipation requirements. The research team’s work addresses how these parasitics manifest at the system level, moving beyond isolated device simulations to evaluate how these technologies perform under real-world AI-accelerator workloads.
Methodology: A Multi-Physics STCO Flow
The STCO flow developed by Benkhelifa et al. provides a comprehensive diagnostic framework that links multiple layers of semiconductor design. By integrating calibrated device models with automated GDS-to-TCAD conversion, the researchers created a pipeline that enables high-accuracy 3D parasitic extraction. This is a significant step forward; historically, designers have relied on simplified RC models that often failed to account for the complex electromagnetic interactions in dense, vertically stacked architectures.
The methodology encompasses three critical pillars:
- Automated Parasitic Extraction: Using GDS-to-TCAD conversion, the flow captures the geometry-dependent resistance and capacitance of A7 and A10 nodes, ensuring that the physical layout accurately informs performance simulations.
- Thermal Analysis: As transistor density increases, power density rises correspondingly. The flow utilizes multi-physics analysis to predict thermal hotspots that could lead to reliability degradation.
- BTI Aging Evaluation: Bias Temperature Instability (BTI) remains one of the primary mechanisms for long-term transistor degradation. By applying physics-based aging models, the researchers were able to project how A7 and A10 devices would behave over years of continuous operation in high-performance computing environments.
Chronology of the A-Node Transition
The semiconductor roadmap has accelerated significantly over the last five years, driven by the insatiable demand for AI compute capacity.
- 2022–2024: The industry solidified the transition to GAA/NSFET architectures. Early adoption began in high-end mobile processors and HPC silicon, establishing the A10/A14-class performance baseline.
- 2025: Research into vertical stacking gained momentum as foundries identified that further lateral scaling was reaching a point of diminishing returns regarding area-per-watt efficiency.
- 2026: The publication of the STCO study represents a maturation of design-for-reliability (DfR) methodologies. The focus shifted from "can we build it?" to "how does it age under sustained load?"
- 2027 and beyond: The industry is expected to move toward pilot production of CFET-based logic, with the insights from this study serving as a guide for standard-cell library optimization.
Supporting Data and Comparative Analysis
The study highlights that while the A7 CFET architecture offers superior area scaling—theoretically allowing for a near-doubling of transistor density compared to A10 NSFETs—the benefits are contingent upon the mitigation of parasitic RCs.
In the comparison between A10 NSFETs and A7 CFETs, the research team observed that the parasitic components in CFETs are not merely smaller; they are structurally different. The vertical interconnects in CFET designs necessitate a re-evaluation of routing strategies. For an AI accelerator implementation, the study found that if parasitic RC values are not optimized at the cell level, the performance gains offered by the CFET’s smaller footprint can be partially offset by increased signal delay and power leakage.
Furthermore, the BTI aging evaluation indicates that the thermal footprint of CFETs is more concentrated. Because the devices are stacked, the heat generated by the top transistor must pass through the bottom transistor or the surrounding dielectric to reach the heat sink, creating a unique thermal resistance profile that differs from the lateral NSFET structure.
Implications for AI Accelerators
The choice of an AI accelerator as the test vehicle for this study is deliberate. AI workloads are characterized by high-toggle-rate logic and sustained high-power states. These conditions are the "stress test" for any new transistor technology.
The findings suggest that for AI hardware, the transition to CFETs will require a fundamental shift in how RTL-to-GDSII flows are configured. Standard cell libraries must be designed with "thermal awareness" from the outset. If designers treat CFETs like traditional planar or FinFET devices, they risk premature chip failure due to localized BTI-induced aging. The STCO flow allows designers to simulate these failure points before the first wafer is ever taped out, potentially saving millions in development costs.
Industry and Academic Perspective
While the paper is a technical collaboration, its implications are being felt throughout the broader ecosystem. Industry analysts note that this type of cross-pollination between academic research and commercial entities like Applied Materials is vital. Foundries require these predictive models to define their Process Design Kits (PDKs).
"The ability to isolate the impact of parasitic RCs while holding the device model constant is a breakthrough for design optimization," noted an independent industry observer. "Usually, you change the node, and you change the model, which makes it hard to see what is causing a performance change. By standardizing the model, this research isolates the ‘geometry tax’ of the CFET architecture."
Future Outlook: Reliability and Scaling
The path to the 1nm node and beyond is fraught with physical uncertainties. As transistors reach the size of individual molecules, quantum tunneling and atomic-scale defects become dominant factors. The STCO flow presented by the team provides a necessary bridge to navigate these complexities.
As the industry moves toward 2027, the focus will likely shift to refining the manufacturing processes for these complex 3D structures. The research suggests that design teams will need to embrace "multi-physics-aware" design environments. This means that CAD tools will no longer just be about area, timing, and power (PPA); they will be about area, timing, power, and reliability (PPART).
The collaboration between TUM, the University of Modena and Reggio Emilia, and Applied Materials demonstrates that the next generation of semiconductor progress will not come from shrinking features alone. It will come from the intelligent, holistic management of the entire system—from the atomic physics of the transistor gate to the thermal management of the full-scale AI processor. By providing a validated framework for this evaluation, the researchers have set a new standard for how the semiconductor industry will assess and deploy the next generation of computing hardware.
