The semiconductor industry is currently navigating one of its most complex transitions as it prepares for the era of High-Numerical Aperture (High-NA) Extreme Ultraviolet (EUV) lithography and the widespread adoption of curvilinear photomasks. As the limits of traditional optical and standard EUV lithography are reached, the ecosystem surrounding photomask technology—encompassing design, data preparation, manufacturing, and inspection—is undergoing a fundamental restructuring. Leading experts from across the semiconductor supply chain recently convened to discuss these challenges, emphasizing that the industry must move toward "curvilinear-native" workflows to maintain the pace of Moore’s Law. The shift is not merely a software update but a complete overhaul of the "Manhattan" geometry paradigm that has dominated chip design for decades.
The Paradigm Shift to Curvilinear-Native Workflows
For decades, semiconductor designs have relied on "Manhattan" geometries—shapes consisting strictly of horizontal and vertical lines. This was a necessity born of the limitations of Variable Shaped Beam (VSB) mask writers, which could only efficiently produce rectangular shots. However, as feature sizes shrink to the single-digit nanometer scale, the physics of light diffraction makes these rigid shapes increasingly difficult to print accurately on silicon wafers.
Inverse Lithography Technology (ILT) has emerged as the solution, using complex mathematical models to determine the optimal mask shape required to produce the desired pattern on the wafer. These optimal shapes are inherently curvilinear. Historically, these curves were "Manhattanized" or broken back down into thousands of tiny rectangles so legacy mask writers could handle them. According to Germain Fenger, Senior Director of Product Management at Synopsys, this "bolting" of curvilinear data onto polygon-based plumbing is no longer sustainable.
The industry is now moving toward a curvilinear-native flow. This transition is enabled by the rise of Multi-Beam Writers (MBW), which use hundreds of thousands of tiny beams to write patterns. Unlike VSB writers, MBW write times are independent of shape complexity, making curvilinear patterns just as fast to produce as rectangular ones. This shift requires the entire mask data preparation (MDP) flow to handle curved data directly, reducing the computational overhead and file sizes associated with fracturing complex curves into millions of tiny polygons.
Computational Challenges and the Role of GPU Acceleration
The move to curvilinear masks and ILT brings an unprecedented demand for computational power. Traditional CPU-based processing is often insufficient for the heavy mathematical lifting required for full-chip ILT. Aki Fujimura, CEO of D2S, noted that ILT is fundamentally computed using Fourier transforms in the pixel domain, a process that naturally outputs curvilinear shapes.
To manage the massive data volumes and the intensity of these calculations, the industry is increasingly turning to High-Performance Computing (HPC) and Graphics Processing Units (GPUs). GPU acceleration allows for the parallel processing of pixel-based data, significantly reducing the Turnaround Time (TAT) for mask production. Furthermore, companies are exploring "caching" strategies, where only the portions of a design that have changed during a re-spin are recomputed, rather than the entire mask. This "incremental" approach to mask data preparation is seen as essential for managing costs as the industry scales toward more complex nodes.
The Chronology of Photomask Evolution
The path to current photomask challenges can be traced through several distinct phases of lithographic development:
- The VSB Era (Pre-2016): Mask making was dominated by Variable Shaped Beam writers. Complexity was limited by the "shot count"—the more complex the shape, the more shots required, leading to prohibitively long write times.
- The Rise of Multi-Beam (2016–2020): Companies like IMS Nanofabrication and NuFlare introduced multi-beam mask writers. This decoupled mask complexity from write time, providing the hardware foundation for curvilinear masks.
- EUV Industrialization (2019–Present): Extreme Ultraviolet lithography entered high-volume manufacturing (HVM). This introduced the need for reflective masks and actinic (at-wavelength) inspection.
- The High-NA Transition (2024–Beyond): The industry is currently preparing for High-NA EUV (0.55 NA), which offers higher resolution but introduces new physical constraints, such as anamorphic imaging and limited depth of focus.
Defect Inspection: The Physics of High-NA EUV
Perhaps the most significant bottleneck in the current ecosystem is defect inspection. As features shrink, the size of a "printable" defect—one that will cause a failure on the wafer—becomes incredibly small. For High-NA EUV, experts such as Harry Levinson, Principal Lithographer at HJL Lithography, warn that printability concerns now apply to features under 15 nanometers.
The industry currently relies on actinic inspection, which uses the same 13.5nm wavelength of light used in the lithography process. This allows inspectors to see the mask exactly as the scanner sees it. However, High-NA EUV introduces a fundamental problem of physics. To achieve higher resolution, optics must capture light at larger angles. Unfortunately, the reflectivity of the EUV mask’s multilayer coating drops off significantly at these larger angles. This loss of contrast makes it difficult for inspection tools to distinguish between a defect and the background noise of the mask.
An alternative is electron-beam (e-beam) inspection, which offers superior resolution. However, e-beam tools suffer from massive throughput issues compared to optical tools. While multi-beam e-beam inspection tools are in development, they face the daunting challenge of separating the return signals from hundreds of individual beams simultaneously.
Redefining Metrology for a Non-Rectangular World
Metrology—the science of measurement—must also be reinvented for curvilinear shapes. In the Manhattan world, critical dimension (CD) was easily defined as the width of a rectangle. On an arbitrary curve, the very definition of "width" becomes ambiguous.
The industry is coalescing around Edge Placement Error (EPE) as the primary metric for curvilinear metrology. Instead of measuring a single width, EPE measures the deviation of a printed contour from the intended design at thousands of points along the curve. This transition requires a move from rule-based checking to simulation-based and statistical approaches.
Glen Scheid, Operations Manager at Micron, emphasized that memory makers and logic manufacturers may approach this differently. In memory manufacturing, where patterns are highly repetitive, statistical averages across many measurements can provide a reliable metric for mask quality. However, for random logic, the challenge is ensuring that every unique curvilinear structure meets the necessary tolerances.
Model-Based Mask Rule Checking (MRC)
As masks become more complex, traditional Mask Rule Checking (MRC) is reaching its limits. Historically, MRC consisted of simple geometric rules, such as "no two lines can be closer than X nanometers." In the curvilinear world, these simple rules are often too restrictive or fail to capture the actual manufacturing risks.
The panel of experts suggested that MRC must become "model-based." This involves simulating the mask manufacturing process—and potentially the inspection process—to determine if a specific shape is viable. Germain Fenger pointed out that many current mask rules are actually dictated by the limitations of inspection tools rather than the mask writers themselves. If an inspection tool cannot reliably verify a shape, the mask shop will often forbid it, even if the multi-beam writer can produce it perfectly. Model-based MRC would allow for more "intelligent" designs that push the limits of what is manufacturable without compromising yield.
Economic and Strategic Implications
The shift to curvilinear masks and High-NA EUV has profound economic implications for the semiconductor industry. The cost of a single EUV mask set can now exceed several million dollars, and the equipment required to produce and inspect these masks costs hundreds of millions per unit.
- Yield Management: With mask costs so high, achieving near-perfect yields is a financial necessity. This places a premium on advanced metrology and repair technologies.
- Turnaround Time (TAT): As designs become more complex, the time it takes to process mask data and write the mask threatens to become a bottleneck in the product development cycle. GPU acceleration and "curvilinear-native" software are the primary defenses against ballooning TAT.
- Conservative Manufacturing: Despite the benefits of curvilinear technology, the manufacturing world remains inherently conservative. As Aki Fujimura noted, "Better is different, and different is bad" in a production environment where any change can risk multi-billion dollar wafer runs. This creates a lag between technical capability and industrial adoption.
Future Outlook: Toward a Unified Ecosystem
The consensus among industry leaders is that the photomask ecosystem is at a crossroads. The transition to High-NA EUV is not just a hardware upgrade but a call for deeper integration between design, software, and manufacturing. The successful adoption of curvilinear technology will depend on the industry’s ability to standardize new metrology metrics like EPE and to deploy the massive computational resources required for ILT.
While the challenges in defect inspection and high-angle EUV reflectivity remain daunting, the progress shown at recent industry conferences like BACUS suggests that the roadmap is intact. The transition to a curvilinear-native world is no longer a matter of "if," but "when," as the industry seeks to extract the final increments of performance from silicon-based semiconductors. As these technologies mature over the next two to five years, they will provide the foundation for the 2nm node and beyond, ensuring that the trajectory of semiconductor innovation continues despite the mounting physical and economic hurdles.
