In a landmark study published in June 2026, a multi-institutional research team comprising scientists from Stanford University, Chalmers University of Technology, HORIBA Scientific, and the SLAC National Accelerator Laboratory has demonstrated a significant breakthrough in semiconductor scaling. The researchers successfully fabricated and characterized monolayer two-dimensional semiconductor (2DS) nanoribbon transistors that achieve unprecedented performance levels at the 25-to-30-nanometer scale. This development addresses one of the most persistent hurdles in the semiconductor industry: the physical and electrical limitations of silicon as transistors approach atomic dimensions.
As the industry moves beyond the 3-nanometer and 2-nanometer process nodes, traditional silicon-based architectures face severe "short-channel effects," where the proximity of the source and drain leads to leakage current and loss of gate control. The research, titled "Scaling nanoribbon transistors with monolayer transition metal dichalcogenides," presents a viable path forward by utilizing Transition Metal Dichalcogenides (TMDs)—materials that are naturally only three atoms thick—to maintain electrostatic control even at extreme levels of miniaturization.
The Push for Sub-5nm Scaling and the 2D Semiconductor Advantage
For over five decades, Moore’s Law has driven the electronics industry toward smaller, faster, and more efficient chips. However, the physical properties of bulk silicon become problematic when the channel thickness is reduced below 5 nanometers. At these scales, surface roughness and quantum tunneling effects degrade performance. To counter this, the industry has transitioned from planar transistors to FinFETs, and more recently, to Gate-All-Around (GAA) nanosheet architectures.
The Stanford-led research suggests that the next evolution involves replacing the silicon channel itself with 2D materials. Monolayer TMDs, such as molybdenum disulfide (MoS2) and tungsten diselenide (WSe2), offer the "ultimate thickness limit." Because these materials are inherently thin, they provide superior electrostatic control, allowing for shorter gate lengths without the parasitic leakage associated with bulk materials.
Despite their potential, 2DS devices have historically been limited to micrometer-scale widths in laboratory settings. Scaling these materials down to nanoribbons—narrow strips of 2D material—often results in edge degradation and delamination during the fabrication process. The new study overcomes these challenges through a specialized top-down multipatterning process.
Innovation in Fabrication: Anchored Contacts and Multipatterning
The primary technical achievement of this research lies in the fabrication methodology. The team utilized a "top-down" approach, which is more compatible with existing industrial lithography standards than "bottom-up" growth methods. To solve the issue of nanoribbon delamination—a common failure where the ultra-thin 2D layer peels away from the substrate during processing—the researchers developed "anchored" contacts.
These contacts serve a dual purpose: they provide the electrical connection to the nanoribbon and physically secure the monolayer material to the underlying dielectric layer. This structural reinforcement allowed the team to scale the channel width and length down to 25–30 nm without losing the integrity of the material.
Furthermore, the integration of thin high-k gate dielectrics was critical. High-k materials allow for a high gate capacitance, which is essential for turning the transistor on and off efficiently at low voltages. By combining these advanced dielectrics with the scaled nanoribbons, the researchers achieved high-performance operation in both n-type (electron-carrying) and p-type (hole-carrying) configurations.
Performance Metrics and Comparative Data
The results published in Nature Nanotechnology reveal that these nanoribbon transistors significantly outperform previous iterations of 2D devices. The researchers tested three primary TMD materials: Molybdenum Disulfide (MoS2), Tungsten Disulfide (WS2), and Tungsten Diselenide (WSe2).
At a drain-to-source voltage of 1 V, the devices delivered the following on-state currents:
- n-type MoS2: 560 µA/µm
- n-type WS2: 420 µA/µm
- p-type WSe2: 130 µA/µm
Particularly noteworthy is the performance of the WS2 nanoribbons. The study reports an improvement of more than two orders of magnitude compared to prior single-gated 2DS nanoribbon reports. Furthermore, the devices achieved "normally off" (enhancement-mode) operation, which is a requirement for modern CMOS (Complementary Metal-Oxide-Semiconductor) logic circuits to ensure they do not consume power when idle.
To verify that the scaling process did not damage the atomic structure of the ribbons, the team employed nanoscale characterization techniques, including tip-enhanced photoluminescence (TEPL). Provided by HORIBA Scientific, the TEPL mapping confirmed minimal edge degradation, proving that the top-down patterning process preserved the high mobility and semiconducting properties of the TMD monolayers even at the edges of the 25 nm strips.
Chronology of 2D Semiconductor Development
The path to this 2026 breakthrough has been a decade-long endeavor in the materials science community:
- 2004–2010: Graphene is isolated, sparking interest in 2D materials, though graphene lacks the bandgap necessary for digital logic.
- 2011–2015: Researchers identify TMDs (like MoS2) as having a natural bandgap, making them suitable for transistors. Initial devices are large and have high contact resistance.
- 2016–2020: Progress is made in chemical vapor deposition (CVD) to grow large-scale monolayers. Early attempts at nanoribbon scaling result in high "edge states" that trap electrons and kill performance.
- 2021–2024: Focus shifts to dielectric integration and "cold metal" contacts. The industry begins exploring "2D-on-Silicon" hybrid chips.
- 2025–2026: The current research from Stanford and partners demonstrates that top-down patterning can achieve sub-30 nm dimensions with industry-leading current densities, bridging the gap between lab curiosity and industrial viability.
Industry Implications and Future Nanosheet Architectures
The implications of this research for the global semiconductor roadmap are profound. As the International Roadmap for Devices and Systems (IRDS) looks toward the 1.5nm and 1nm nodes, the integration of 2D materials is no longer viewed as optional but as a likely necessity.
Industry analysts suggest that the success of the "anchored" contact method could influence the design of future Nanosheet Field-Effect Transistors (NS-FETs). In current GAA architectures, silicon or silicon-germanium sheets are stacked vertically. Replacing these with TMD nanoribbons could allow for even denser stacking, reduced heat dissipation, and higher switching speeds.
The participation of SLAC National Accelerator Laboratory underscores the importance of advanced imaging in this field. Using high-energy X-ray characterization, the team was able to observe the interface between the 2D material and the metal contacts at the atomic level, providing data that will be crucial for semiconductor foundries like TSMC, Samsung, and Intel as they evaluate these materials for mass production.
Expert Analysis: Overcoming the "Edge Effect"
One of the most significant findings in the paper is the mitigation of edge degradation. In nanomaterials, the atoms at the edge of a structure often have "dangling bonds" that create electronic noise and scatter charge carriers. In previous attempts to create nanoribbons, these edge effects were so dominant that the performance of the transistor plummeted as the width decreased.
By utilizing the top-down multipatterning process and precise characterization via TEPL, the Stanford-led team proved that TMD nanoribbons can maintain high-quality crystalline structures right up to the boundary. This suggests that the theoretical limits of 2D materials are much higher than previously thought, and that the practical limits are dictated by fabrication precision rather than the physics of the material itself.
Looking Ahead: The Road to Commercialization
While the results are promising, several hurdles remain before 2D nanoribbon transistors appear in consumer electronics. The first is "wafer-scale" uniformity. While the researchers demonstrated excellent performance on individual devices, scaling this to billions of transistors on a single 300mm wafer with 99.9999% yield is a massive engineering challenge.
Secondly, the integration of p-type TMDs continues to lag slightly behind n-type counterparts. While the 130 µA/µm achieved for p-type WSe2 is a significant step forward, achieving perfect symmetry between n-type and p-type performance is essential for the most efficient CMOS logic.
The collaboration between Stanford, Chalmers, HORIBA, and SLAC provides a blueprint for the kind of interdisciplinary work required to solve these problems. By combining material science, advanced lithography, and state-of-the-art optical characterization, the team has moved 2D semiconductors out of the realm of theoretical physics and into the foreground of next-generation transistor technology. As the semiconductor industry enters the latter half of the 2020s, these 2DS nanoribbons stand as a primary candidate to succeed silicon, ensuring the continued advancement of computing power in the AI era.
